1. Field of the Invention
This invention relates to the field of data processing apparatus having data stores including both caches and memory. More particularly the invention relates to interconnect circuitry for these data processing apparatus, the interconnect circuitry providing data routes via which one or more initiator devices such as a master may access one or more recipient devices such as a slave.
2. Description of the Prior Art
Interconnects are used to provide connections between different components in data processing systems. They provide data routes via which one or more initiator devices may access one or more recipient device. An initiator device is simply a device that generates a transaction request, and therefore may be a master such as a processor or it may be another interconnect. A recipient device is simply a device that receives the transactions and it may be a slave such as a peripheral or it may also be another interconnect.
As systems become more complex with multiple processors communicating with each other and with multiple devices, and with different storage facilities including both caches providing fast data access and memory, authors writing software for multiprocessor systems need detailed knowledge of the topology and latency of an architecture, in order to write software which ensures consistent behaviour of interacting processes across time. Even with this detailed knowledge this consistency is only achieved with some non-trivial effort and cost to performance.
It would be desirable to provide mechanisms that allowed a programmer to ensure consistent behaviour of interacting processes across time in a generic manner for an arbitrary architecture.
There are particular problems associated with data store maintenance operations in complex systems with arbitrary architectures as it is important to know when these operations are complete and yet if the system is not sure of the number or arrangement of the data stores, then this may be difficult to track.
For example in a system having multiple caches at least some of which can be accessed by more than one master, it will be difficult to determine for any cache maintenance operation that maintains the caches when this maintenance is complete without a detailed knowledge of the architecture and in particular, of the number and arrangement of the caches. Thus, data store maintenance operations provide a particular problem when designing architecturally agnostic systems.
This application claims priority to GB Application No. 0917946.5 filed 13 Oct. 2009, GB Application No. 1007363.3 filed 30 Apr. 2010, GB Application No. 1007342.7 filed 30 Apr. 2010 and GB Application No. 1016482.0 filed 1 Oct. 2010, the entire contents of each of which are incorporated herein by reference.